It is common, in the transmission of digital data, to process the data bits to be transmitted to render the transmitted data bit stream less vulnerable to jamming. Typically, consecutive data bits provided for transmission are supplied to a convolutional interleaver and therein are spread apart in transmitted data bits by J+1 interleaved data bits, J being an integer below defined. However, a pulse jammer with a repetition period of J+1 data bits will cause the deinterleaver of a receiver to output sequentially jammed data bits as received data bits
The foregoing problem can be overcome by operating the interleaver in pseudo random number (PN) mode. In this mode, every group of data bits to be interleaved is simultaneously pseudo randomly reordered, by different pseudo random sequences. The J+1 periodicity is accordingly eliminated from the interleaved data bit stream transmitted and the stream is consequently not vulnerable to pulse jamming.
One known type of I, J fixed convolutional interleaver comprises a system involving l delay paths, with the initial path producing no delay, i.e., having no delay cells, but with consecutive path each introducing nj delay cells, where n is the number of the paths in the succession and j is the individual cell delay value. The J term associated with the standard I, J fixed convolutional interleaver is given by the product of j*I.
Referring to FIG. 1, this type of fixed convolutional interleaver system FCIS has paths FCIS0, FCISl, FCIS2, FCIS3, etc., through to path FCIS (I-1). Path FCIS0 has no delay. Path FCISl has a single delay cell FCISl-1 of time length j. Path FCIS2 has two delay cells FCIS2-Ia, -1b,each of time length j; providing a total delay of 2j. Path FCIS3 has three delay cells FCIS3-1a, -1b, -1c, each of time length j, providing a total delay of 3j. The structure continues progressively to end path FCIS (I-1), which has I-1 delay cells, with total delay of (I-1)j.
Hardware implementation is of course of paramount consequence to cost and speed of operation of interleavers and deinterleavers, the latter reversely replicating the former and being of like hardware composition.
In the FIG. 1 type system, shift register elements realize the delay cells. The total number of shift register elements required for this implementation amounts to one-half of the product of (I-1) and J. Another known type of convolutional interleaver employs random access memory to realize the data bit interleaving. This type of system involves considerably more storage element requirements, almost twice that of the shift register element implementation, i.e., the product of I and J.
Disadvantages of the first discussed type of interleaver are its invariance and the number of discrete components required for large I and J values. Thus, it is hardware implemented for handling preselected and unchangeable values for I and J.
A disadvantage of the second discussed type of interleaver is its memory requirement, as noted, almost twice that of the first type of system.
More importantly, both implementations are susceptible to periodic jammers.